Hallo Andre,
I want to work out the idea to use a 74LS612 in combination with the 6510.
The TI-databook is not very clear so I want to put everything (I think) I
know about the 612 on paper so you (or anybody else) can correct it. Later
we can use the resulting script as extra info for people visiting our
sites.
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74LS612
The 612 is an IC that enables you to expand your system with 8 extra
addresslines. Notify the fact that I use the word "system" and NOT
processor. The processor won't be aware of those extra addresslines. In
case of the 6502/6510 the processor still only can address 64 KB.
How do these 8 extra addresslines fit in the system?
If you own a C128 then this is easy to understand. The C128 has 128 KB of
RAM, 4 KB of I/O and a lot more ROM. A part is accessed by means of the
PLA, another part is accessed by means of the MMU (Memory Management Unit).
The MMU can be manipulated by its own onboard registers by means of the
Basic-command "BANK". You can choose from 16 banks which is equivalent to
four addresslines. But these extra lines are not visible to the user and
lead straight away to some onboard multiplexers which on the end produce
the needed ChipSelect-signals.
The C64 has an MMU as well. But in the case of the C64 this MMU is the
combination of a part of the onboard I/O port of the 6510 and the PLA. In
this particular situation you can consider those I/O lines as extra
addresslines.
The 74LS612 is a kind of MMU but WITHOUT the multiplexers. These have to be
added by the user. Another difference is that the behaviour of the MMU is
preprogrammed in the factory and cannot be changed. But with the 612 the
user can program its behaviour any time. Speaking in MMU-terms this would
mean that we could program the MMU in such away that BANK 0 behaves like
BANK 3, BANK 3 and 1 as 1 and BANK 2 as 1 as well.
The 612 has 16 registers of 12 bits each. The normal procedure is to
address these registers by four addresslines. Four bits of the output are
used to replace the original four addresslines, the other eight bits to
form the extra eight addresslines.
Reconfiguring the original addresslines gives you the possebility to re-
arange the internal configuration if the hardware. By example in a PET you
could swap the the range $7000/$7FFF and $F000/$FFFF to test a new Kernal-
ROM.
The extra eight lines can be used to add extra memory (RAM, ROM) or I/O in
any way you want. A very nice example is to connect a complete 1541 to your
own system by means of a small interface which replaces the original 6502.
Now you can reconfigure your own system in such a way that it sees the
range $0000/$BFFF of the 1541 as its own and its former own area
$6000/$9FFF as area $C000/$FFFF. In this way you comfortably can test a new
Kernal for the 1541.
Pinouts.
+---------------------+
RS2 -+ 1 40 +- +5V
| |
MA3 -+ 2 39 +- MA2
| |
RS3 -+ 3 38 +- RS1
| |
CS -+ 4 37 +- MA1
| |
STROBE -+ 5 36 +- RS0
| |
R/W -+ 6 35 +- MA0
| |
D0 -+ 7 34 +- D11
| |
D1 -+ 8 33 +- D10
| |
D2 -+ 9 32 +- D9
| |
D3 -+ 10 31 +- D8
| 74LS612 |
D4 -+ 11 30 +- D7
| |
D5 -+ 12 29 +- D6
| |
MM -+ 13 28 +- NC
| |
MO0 -+ 14 27 +- MO11
| |
MO1 -+ 15 26 +- MO10
| |
MO2 -+ 16 25 +- MO9
| |
MO3 -+ 17 24 +- MO8
| |
MO4 -+ 18 23 +- MO7
| |
MO5 -+ 19 22 +- MO6
| |
GND -+ 20 21 +- ME
| |
+---------------------+
Pin functions:
D0 thru D11 Connection to the databus when programming the registers
RS0 thru RS3 Connection to the addressbus when programming the
registers, normally A0 thru A3
R/W Read, active (H) and Write, active (L)
STROBE input to enter data into choosen register, active (L)
CS ChipSelect, active (L)
MA0 thru MA3 connection to the addressbus during normal operation
MO0 thru MO11 The generated addresslines
MM Map Mode input. When (H), MO0/MO3 reflect MA0/MA3,
MO4/MO11 are (L). When (L), MO0/MO11 reflect the 12 bits
of the choosen register.
ME When (H), MO0/MO11 are tristate else active.
NC Not connected.
74LS610, 74LS611 and 74LS613.
The 610 is an 612 plus an extra 12 bits latch. With the 612 MO0/MO11 always
react on the behaviour of MA0/MA3 and MM. With the 610 you can freeze the
output as long as you want. This is archieved with an extra inputline at
pin 28, C (= Clock). A (H) on this input will the 610 behave like a 612, a
(L) freezes the configuration.
The 611 and 613 are the Open Collector versions of the 610 and 613.
The 12 bits registers of the 74LS612.
The intention is to use the 612 in combination with a 6502 based Commodore
and as you know these are all 8-bitters. This means we either have to
disregard 4 bits or use a trick to be able to use all 12 bits. In the first
case we are still able to address up to 1 MB of memory or I/O. If you still
want have those extra 4 bits then a simple 74LS373 will do. Of course
you'll need a decoder for this 373 but as you need one for the 612 as well,
it won't be that much difficult to combine them into one decoder.
Connecting the 612 to a 6502.
Connecting a 612 to a 6502 can be split up in two parts anyway: the memory-
part and the I/O-part.
Memory-part.
If you only want to reconfigure your system within its own 64 KB, then you
only have to "cut" the addresslines A12 thru A15 and to place the 612 in
the created gap. Practically this probably means you replace the processor
by a small circuitboard with onboard the original processor, the 612 and
some logic to perform I/O-operations with the 612.
If you want to use the extra addresslines as well, you have to take care of
the fact that the original hardware does not respond to addresses above
$0FFFF. The original does not know the extra addresslines so to any decoder
the address $0C000 is equal to $1C000, $2C000 and so on. IMHO the solution
for this problem is to disable Clock2 towards the original system. As far
as I know all decoders and/or I/O-ICs in any Commodore use this signal to
decide to become active or not.
I/O-part
The decision to be made is where to place the decoder for the 612 itself:
behind or before the 612. If you place it before the 612 it always will be
accessible but the disadvantage is that it can get it the way when there is
a need to remap certain areas to the area the 612 occupies. If you place it
behind the 612 and you make a mistake with programming the 612, it is
possible you cannot acces the 612 at all anymore meaning you are stuck with
the momentary configuration unless you reset your system.
Practical use.
Andre Fachat built a 4 MHz 65C02 based computer, <A HREF=''>the CS/A65</A>,
using the 74LS610. Some of the above info and ideas are based on his work.
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Questions:
1) Why do you use a 610 as you don't have any specific use for the
onboard latch? (Answer: because I just happened to have one ???)
2) Why do you use IC16 to disconnect the 610 from the bus instead of
using the 610s own capability to do so?
3) You placed the decoder for the 612 before the 612 meaning you always
can access the 612 on the same address, $E800, whatever the
configuration is. On the other hand you say you use your CS/A65 to
test new ROMs for the 1541, meaning you need the whole range from
$C000 thru $FFFF. This is an conflicting situation.
I noticed you have a inputline to disable IOSEL. Activating this line
when you address the area $C000/$FFFF when testing the 1541 ROM means
you are stuck to this configuration until a reset.
How do you handle this particular situation?
4) Why do you use 245s instead of the more power friendly 541?
At the moment I'm working out an idea of combining a 65816 and a 74LS610.
Groetjes, Ruud
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