From: Spiro Trikaliotis (ml-cbmhackers_at_trikaliotis.net)
Date: 2006-05-11 20:54:32
Hallo list,
I have been asked to forward this mail to here. Ok, here it is:
---- snipp -----------
for high precision RPM measurements of the 1541 disk drive, I'm
thinking about using the timers provided by the both VIA chips.
Since a complete disk rotation roughly needs 200000 clock
cycles, but one 16-bit timer is only able to do 65536 counts I
thought I could use linking two of such timers together as it
can be done with the 6526 CIA.
But this will not work since you can't configure it with the
6522 chip.
So what I am now thinking on is to use the serial shift register
as an additional high order 3 bits counter (shifting a unique
bit pattern in Mode 100, Free-Running Output), thus retrieving a
true 19 bits hardware counter driven by a clock rate of 1MHz.
With a maximum count value of 524288 it will cover more than two
complete disk rotations.
Still there are many detail tasks to be solved:
* CB1 and CB2 may be connected to otherwise important
functions of the 1541 disk drive and may produce wierd
things, if they are used as bitshift output or clock
output registers
* In fact, the shift register is driven by the low order
8 bits of timer 2, not by the whole 16 bits of the
timer. But this can be circumvented I hope by using a
prime number or otherwise a number not dividable by 8
(the shift register maximum count value) for the high
order timer byte, maybe 255 or 251 (prime):
==> In the end, the shift register should contain
another value on each timer2 underflow, but it
would need some postprocessing to recalculate
the virtual highest order byte of bits 16...23.
* There is the VIA shift register bug that was called to
_interfere_ with other chip functions as Jim
Butterfield said once
On the last topic I probably found a much more detailed
explanation in the forum of 6502.org, originated by Garth
Wilson:
http://www.6502.org/users/garth/projects.php?project=1&schematic=11
http://www.6502.org/forum/viewtopic.php?t=40&highlight=wd65c22s&sid=1b6df141e8909b4e07790e40fe9adf84
My questions now would be:
Is this a suitable explanation?
Is this the _only_ bug regarding the shift register?
In the net I found more docs talking about race conditions
between the timer and IRQ of the VIA6522, does anybody know
more about this?
And now to you Nicolas, recently we talked about CMD's (Creative
Micro Devices, not California Micro Devices) FD2000 disk drive
and how it did implement the fast serial bus (Serial Burst). On
an image you sent to me there was only one single 6522 VIA chip
used as general I/O with no other chips that could implement the
fast serial protocol.
Further you told me something about that CMD was proud to have
solved the VIA6522 bug?
As the posts from above are telling that the VIA bug is
contained in nearly all derivatives, I now wonder _how_ CMD did
work around it. Was the CMD G65SC22 (now California Micro
Devices, not Creative) fixed in this and only a few people do
know or did CMD (Creative ...) apply some soft of external patch
as proposed in the forum discussion from above?
Nicolas, maybe you are willing to trace down the both
handshaking lines CB1 and CB2 from the VIA G65SC22 to find out,
if these are connected to the IEC port "directly" (I think they
are bidirectionally buffered as in the 1571) or if there is a
D-FlipFlop brought into, if the serial shift register is put
into externally clocked input mode. I assume (or do I know ;-)
there is a 74LS74 TTL somewhere on the board?
---- snipp -----------
Most interestingly (for me), it was the first time I saw someone really
explain what these 6522 bugs are. I would be very interested about info
on the other mentioned ones in the links. Does anyone know anything
about them?
Regards,
Spiro.
--
Spiro R. Trikaliotis
http://www.trikaliotis.net/
http://cbm4win.sf.net/
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