From: Jim Brain (brain_at_jbrain.com)
Date: 2007-12-13 08:34:33
ruud.baltissen@abp.nl wrote:
> Nope, A5 is just needed to read/write the High byte of the data ie.
> D8..D15. Have a look at IC7A, the first half of a 139, you will see that
> both A5 and R/W are responsible for selecting the 573's. In fact only
> the addresses $20 and $30 are used, the rest are mirrors of those two
> addresses.
>
I understand. And, I think your argument that placing the hi byte a
ways off is very valid, as it takes the same amount of code to load 16
byte values either way, but your approach saves a lot of time when
loading a string of 8 bit values to registers. Thus, I'm convinced.
But, as we discussed, I did change the IDE16 design slightly. Instead
of putting the hi byte after both sets of IDE registers (IDE1 and the
phantom IDE2), I modified the design so that IDE1 low registers are
followed by the hi byte, mirrored, followed by the IDE2 addressing,
followed by the hi byte again. For the others, I feel like this uses
the memory map more sparingly, as a design could use 32 bytes for the
IDE interface and then decode the next 32 bytes for something other than
a secondary IDE interface.
> If it was up to me, I would start in the same way as I did with the
> 1541: soldering the interface and trying to make this work first only
> using a BASIC program. My question: is it possible to force a program up
> on the FDC of an IEEE drive ???? That I really would like to know!
> The IEEE drives have a big advantage: a sepperate FDC. IMHO this means
> we can adjust the ROM so the FDC is able to handle an harddisk without
> having to alter the software for the other 6502. Remark: don't forget
> that the ROM for this 6502 contains some routines meant for the FDC.
>
As noted earlier in PM, I think the 8250 folks should get this board,
plug it in, and make a small perfboard to do the SELect.
Here's what I did thus far:
Merged your IDE8 and IDE16 schematics into 1 design. I used the address
select and such from the 16 bit design (very clever, I must say), but
used the '244 and NAND gates for the inverters, as I wanted to drop the
'138 from the IDE16 design and found I could do so by doing:
/(/(/SEL)*PHI2)
This gives me an active low when SEL is low and PHI2 is high.
By merging the designs, I was able to get to 6 ICs (ditched a 139), and
had some room left over. So, with the extra room, I added a C64
expansion port connector and wired lines up as appropriate.
I can't take credit for the design, but I am happy with the merge. Out
of the design, I got:
* Ruud's 8 bit interface
* Ruud's 16 bit interface
* Poor man's IDE64 interface
in 2.6x3.6" of board. 9 will fit on a panel, so I can spin 18 boards.
I tried to hook up all the 6502 lines to the C64 connector, so someone
could use it on the '41 as an expansion port or could wire an EPROM into
it for 64 use, but ran out of room for traces and I didn't want to start
going to more esoteric lengths to get all the lines to fit.
I know a few volunteered to look at the design. I think this is the
final one, and I put pics up at:
http://www.jbrain.com/vicug/gallery/1541ide
I'd appreciate some eagle eyes, comparing the board to Ruud's initial
designs. Let me know, and I can potentially spin the boards this week.
Oh, and Merry Christmas. Al Anger has offered $100 towards the cost of
the run. Thus, the first $100 of boards will be given away. To be
fair, probably 1 free board, and additional ones at cost. It looks like
5-5.50/board at the run rate I anticipate.
I have 6 boards spoken for thus far, not counting the 2 folks who wanted
more than 1 board. Any others?
Jim
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