ruud.baltissen_at_apg.nl
Date: 2008-07-31 15:22:04
Hallo allemaal,
Looking a bit further to find out how all those little routines are
used, I ran in another mistery.
StepHead ;
[FA05]
lda STEPS
bpl B_FA0E
eor #$FF
clc
adc #$01
B_FA0E
cmp MINSTP ; fast stepping?
bcs B_FA1C ; yes, ->
lda #<(E_FA3B)
sta NXTSTzp
lda #>(E_FA3B) ; pointer $62/$63 to
$FA3B
sta NXTSTzp+1
bne J_FA2E ; always ->
If the drive decides to go slow-stepping, the interrupt routine is
tweaked to $FA3B, see above.
J_FA2E lda STEPS ; step counter for head
transport
bpl B_FA63
inc STEPS ; increment
ldx PortB2
dex
jmp J_FA69
;** Move stepper motor short distance
E_FA3B lda STEPS ; step counter for head
transport
bne J_FA2E ; not yet zero?
....
B_FA63 dec STEPS ; step counter for head
transport
ldx PortB2
inx
J_FA69
txa
and #$03
sta TMP
lda PortB2
and #$FC
ora TMP
sta PortB2
jmp J_FABE
As long as there has to be stepped, at $FA3B the routine goes to $FA2E.
There the output of the 6522 is updated. At the next interrupt, $FA3B is
called again and again the 6522 is updated. My mistery: WHERE IS THE
DELAY BETWEEN THE STEPS ????? I'm sure I missed something but what and
where?
--
___
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/ / |_/ Groetjes, Ruud
\ \__|_\
\___| URL: Ruud.C64.org
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