Hallo Michael,


Sorry for the delay but I hoped for anyone to answer who knows more
about the stuff.

 
> How does the VIC refreshs the RAM? According to the VIC article it
> generates an address and does a write?

I'm quite sure that this is NOT the case. The DRAMs in the C64/128 have
a multiplexed address bus. You offer the address in two parts: the Row
Address and Column Address. No schemtic at hand but IRRC two 74LS257's
take care of splitting the address in two in the C64. Negating either
the RAS input or CAS input (S = Select) tells the DRAM which part of the
address is valid.

To refresh a DRAM only the Row Address is needed and it has to be done
in READ mode. 
The older C64's use 200 ns. DRAMs. This means they can be read/written
within 200 nanoseconds. BUT then the DRAM needs a recovery time of at
least 150 ns. This totals 350 ns. which fits nicely inside the 500 ns.
of a half clock cycle. But this means there is no time for a normal read
and a refresh within a half clock cycle. OTOH this refresh cycle is not
needed every clock cycle. And how the VIC combines the refresh and his
real work, I have no idea.


> Can I do this also via VPU by reading or writing certain addresses?
> If yes, what memory addresses are refreshed if I read a 
> certain address?

You can refresh the DRAM just by reading certain addresses. Just find
out what address lines are connected to the DRAM by 74LS157. I have seen
a small 6502 machine whose adress lines A0..A7 where used for RAS and it
run a wait loop where 256 bytes only contained the instructions "LDA
#$FF". As these 4164's only needed to be refreshed within 2 ms., he had
roughly one ms. to do the actual job.

I hope this helps a bit.


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