Re: 6809 assembly knowledge needed

Jim Brain wrote:
> I've been teaching myself Verilog tonight, and I have made the design I
> wanted in the language.  Still, it'd be nice to know who on-list might
> be able to answer questions, as I have plenty.

I really liked the Ciletti book, Advanced Digital Design with the
Verilog HDL.

> What caught me tonight was this:
> 
> output wire p1_io1,p1_io2
> reg [7:0] config
> input wire io1,io2
> 
> // allow p1_io1 to go low when selected (config[0] = 0) and io1 is low
> and swap (config[2]) is low, or if config[2] is high and config[1] and
> io2 are both low
> 
> // this works
> assign p1_io1 = (CONFIG[0] | io1 | config[2]) & (config[1] | io2 |
> !config[2]);
> 
> // this does not:
> always @(io1 or io2 or config1[2:0]) begin
>      case(config1[2])
>         1'b0:  begin
>             p1_io1 = io1 | config[0];
>             p1_io2 = io2 | config[1];
>           end
>         1'b1:  begin
>             p1_io2 = io1 | config[0];
>             p1_io1 = io2 | config[1];
>           end
>      endcase
>    end
> 
> I thought the latter was easier to read, but to use it, p1_io1 and
> p1_io2 have to be declared as reg.  I have a philosophical issue with
> that, as I view "reg" as a register, and I don't think the CPLD/FPLGA
> needs to dedicate a precious register to the value of p1_io1, etc.  I
> see in the documentation/web pages that the tool should determine that
> no state is kept, so it will just turn the case statement into
> combinatorial logic, but it worries me.

The reason is that all outputs have to have registers declared. This
allows the synthesis tool to first treat each block and its in/out ports
separately, then apply the optimizer to inter-block relationships. The
tool never wants you to be surprised when something gets registered and
you didn't know it (i.e. a phantom register hiding behind an output wire
declaration).

The assign works because it is not a logic block. Assigns can only ever
be combinational logic.

Bil is right when he says reg does not mean you'll actually get
flip-flops allocated. In your case above, I believe the optimizer will
do intermediate register elimination when it checks the dependencies and
p1_io* would not be allocated a register.

> The final solution I used was:
> 
> assign p1_io2 = config[2] ? io2 | config[1] : io1 | config[0];

That seems fine and perfectly readable.

-- 
Nate


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