On Mon, 23 Aug 2010, Groepaz wrote: > On Montag 23 August 2010, you wrote: >> On Mon, 23 Aug 2010 Ruud@Baltissen.org wrote: >>> Regarding the model, it is in fact based on my TTl6502. And Gideon >>> couldn't detect any flaw :) Using this model I discussed my finding >>> that IMHO all the cores I know, including Gideon's, treated NMI as >>> level triggered. The docs state that the NMI in the 6502 is edge >>> triggered. He agreed with my findings. But so far it never caused >>> problems, so why changing it? I gave him an example where things >>> could go wrong. Anyway if the docs state edge triggered, why not >>> implementing it? >> >> How would the NMI even work if it is implemented as level triggered? >> It's _non_ maskable. If strictly level triggered it will just endlessly >> retrigger the interrupt with no chance to ack, no? > > and thats what happens actually, and its why there is a RC element wired to > the restore key :) That's because the restore key would generate bounces (= repeated edges). There's no RC on the path from the CIA/VIA, so an emulation implementing NMI as level triggered wouldn't work well with a CIA/VIA. My guess is that these newer cores implement synchronous edge triggering instead of level triggering. I.e trigger an interrupt when the level changes to active between two subsequent clock cycles. /Daniel Message was sent through the cbm-hackers mailing listReceived on 2010-08-23 20:00:33
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