Small correction... 64kbits chips, although the multiplexed address input is 8 bits wide, still need 7-bit refresh counters (128 refresh cycles). 8 bit refresh counters and above are needed from 41464 and 41256 (64kx4, 256kx1 = 256kbit) and on. Greets, Levente On 2011-01-25 23:29, Hoffmann-Vetter, Martin wrote: > Hello, > >> $A1 end $21 have >> 7 bits in common; exactly the number of address lines of a 4116 >> DRAM. > > It's 4164 DRAM! That must be used with 8 bit refresh (256 refresh cycle) and the CBM-II has a 8 bit refresh counter (74LS393). > > Greetings > > Martin > > > Message was sent through the cbm-hackers mailing list > Message was sent through the cbm-hackers mailing listReceived on 2011-01-26 12:00:09
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