Hallo Jim, > The current logic looks to require a couple '00 and .... > I'm wondering if someone is interested in simplify that logic I ran into the same problem with my CBM-HD project. I have two soultions: 1) http://www.baltissen.org/images/xieee5.png using three 7406 gates. Pin 17 of a LPT port is an OC output. If none available, use one of the left-over gates of the 7406 IC. 2) http://www.baltissen.org/images/xieee1b.gif using three (or four) BC547 transistors. Explanation, taking xieea5 as example: There are two situations: - the ATN-trap is active = output is (H) If ATN is not active = (H), then the output of IC2a = (L). Which means the outputs of 2b and 2c are (HiZ) and effectively don't do anything. The moment ATN becomes active (L), output 2a becomes (H), which on its turn make both 2b an 2c active (L), telling the master system to wait. - the ATN-trap is inactive = output is (L) The moment ATN is active, the slave system must respond to the master but can oly do it by using NRFD and NDAC. By pulling the inputs of 2b and 2c (L), these two lines are "freed" again. Hope this helps :) -- ___ / __|__ / / |_/ Groetjes, Ruud Baltissen \ \__|_\ \___| http://Ruud.C64.org Message was sent through the cbm-hackers mailing listReceived on 2011-06-14 07:00:13
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