Re: Additional SIDs

From: "Rainer Buchty" <rainer@buchty.net>

> I don't know the C64's timing well enough to judge whether it will work 
> w/o hassle to feed the VIC's dotclock (being close to 8MHz) into the DOC 
> and just use a bunch of Phi2-driven 74245 to attach it to the bus. 
> Presumably, Phi2 and the DOC-generated E clock need to be combined into a 
> common gate signal in order to avoid bus collisions.

That looked like the easy option at first glance, but now you've explained 
the DOC expects to be bus master and generate the other CPU clocks, I think 
the easiest thing to do would be to have another PLL and generate more or 
less a copy of the VIC-II dot clock but with timing to suit the DOC. So, the 
PLL would compare the divided down E or Q clock coming from the DOC with the 
phi 2 signal coming from the C64, and control an 8MHz VCO for the DOC so as 
to keep those two in sync.

You'd end up with a C64 having one 14.3MHz or 17.7MHz crystal and two 8MHz 
PLLs, one inside the machine and one on a cartridge connected to the 
machine, but I think it could be persuaded to work.

> In worst case, of course, some mailbox-like solution should work, which 
> however would make reading DOC registers somewhat more complex.

Reading the DOC registers should be possible with the PLL solution assuming 
the DOC read cycle (meant for 6809) is compatible with 6502.

> Of course, you also will need 128kB of sample RAM (if you go for a single 
> audio channel, then up to 2MB of sample RAM, 1MB for stereo, is possible 
> by abusing the channel address bits as additional wave address bits).

As I understand it the basic DOC has a 64K address space and a bank select 
bit (i.e. A16) for every oscillator. I was actually thinking of sample ROM 
for a simple C64 implementation, using either the 64K ESQ-1 ROM or perhaps 
half the 256K SQ-80 ROM. I think the Apple IIGS has 64K of sample RAM, 
possibly DRAM, and bus arbitration logic to write to either DOC registers or 
sample RAM. But because the DOC has no method of writing to RAM itself, all 
logic to select which memory addresses to write to have to be external to 
the DOC.

> I do have some spare DOCs, so if there's sufficient interest I could be 
> talked into donating some for hacking purposes. Would be fun to see what 
> further capabilities reside in that chip (apart from the sync bug).

The implementation questions I'd want to answer: can a digital oscillator 
chip with 8 bit samples and phase accumulating oscillators sound good - i.e. 
as good as SID in the aliasing department. Is sample ROM enough to make a 
musically useful instrument (I like my ESQ1!), or does it have to have RAM 
to be useful, and how much more complex is the logic needed to write to RAM. 
How many output channels to support, 1, 2, 4, 8 or 16. Each output channel 
needs a sample and hold circuit and a low pass filter.

Richard 


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