On 02/23/2012 02:42 AM, Jim Brain wrote: > On 2/22/2012 1:42 PM, Gerrit Heitsch wrote: >> >> The idea with the cap was not to stretch the cycle but to filter out >> short voltage spikes (line noise). The value was a guess back then, >> but if you omit it, your clock will be fast (that part was tested). > That's my digital side peeking out. Never thought about line noise on > the TTL. Well, the problem is kind of on the digital side... All involved circuits from the optocoupler to the clock counter are fast enough to consider a 1 ms or shorter spike on the input as a valid pulse. Those happen quite often on the power grid. The first 74LS14 gate will make the sorta half sine wave into a proper square wave, the capacitor will slow the rise of its output to some degree since it needs to be charged. So if the pulse on the input is short enough, it won't be long enough to lift the input of the second 74LS14 over the threshold and the pulse won't be seen by the clock. Again, directly hooking up a capacitor of that size to a TTL output stage is not recommended, but in my case it worked for years without any problems. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2012-02-23 17:00:34
Archive generated by hypermail 2.2.0.