Re: 6502 bus timing

From: Michał Pleban <*lists_at_michau.name*> Date: Wed, 25 Apr 2012 17:36:40 +0200 Message-ID: <4F981A08.2060101@michau.name> · lists_at_michau.name

Hello!

Baltissen, GJPAA (Ruud) wrote:

> No, it is the address that should valid and stable on the rising edge. I was told that that is needed for the 6522 for example, maybe other 65xx ICs as well? That's why you need a trick to connect the 6522 to a C64.

OK, but in the context of reading from a device: you have a rising edge 
of PHI2, and you know that the address is valid on the bus. If I am a 
device, I should now post the data immediately on the bus, so the CPU 
can get it on the falling edge, right?

Regards,
Michau

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