A couple observations: 1) The 6702 has an input for the system reset. This means that the 6702 must have one continuous sequence, OR, there is a software reset command for the 6702. 2) A hardware chip of this size would have a response time of 50 micrseconds, or less. PEEKing and POKing from BASIC may not be fast enough to see all the output. 3) The 6702 is connected to phi2. I may be capable of responding after a predetermined number of clock cycles, or of resetting if the correct sequence is not received in a predetermined interval. wlevak@sdf.lonestar.org SDF Public Access UNIX System - http://sdf.lonestar.org Message was sent through the cbm-hackers mailing listReceived on 2012-04-30 05:00:25
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