Re: Broken TED for visual6502.org

On 07/15/2012 02:26 AM, Segher Boessenkool wrote:
> On 14-jul-2012, at 19:03, Gerrit Heitsch wrote:
>> On 07/13/2012 12:42 PM, Ingo Korb wrote:
>>> Gerrit Heitsch <gerrit@laosinh.s.bawue.de> writes:
>>>
>>>> Not that I can make out anything that looks like it's the cause for the
>>>> chip no longer working.
>>>
>>> The structures at the lower left side, fourth pin from the bottom look
>>> like they may be damaged.
>
> (That's the A7 pin).
>
>> Yes, but that looks to me like something that happened during the
>> removal of the plastic covering the die. Remember they use hot acid to
>> do this. The die only survives that due to the passivation layer
>> (SiO2, meaning quartz AFAIK). Unfortunatly, you can't cover the
>> bonding pads with it so depending on the tolerances the damage there
>> might just have been some acid getting where it shouldn't have gone.
>
> I agree with Ingo, this doesn't look like it is caused by the decapsulation
> processing: at many of the pads you see damage to the metal, but it looks
> different.  Firstly, it is closer to the pad opening than you see near A7;
> secondly, you don't see that black colouration you have at A7; thirdly, the
> metal on the pad at A7 looks like it has melted (you don't see damage to
> the metal on the pad at all at the other pads, except when it has been
> physically ripped away).

Hm, on the lower row of pads I find damage that looks very similiar, 
just not as extreme though. There is also some blackening here and 
there. Maybe the passivation layer near A7 already failed during the 
lifetime of the CPU and allowed the acid to do more damage during 
depackaging.

Also when you look at the layer 'counter', you can see what looks like 3 
cracks in the die. Could just be the lighting and the passivation layer 
though.



> Some other observations...  This chip has all the pads it needs to function
> as an 8500 or 8502 (#NMI, PHI2 out).  The third pad from the left on the
> top is not used by any of these chips; it is an output, I'm guessing
> this is SYNC.  The chip has pads for only seven of the Pn port bits;
> I'm thinking the space for the eighth was sacrificed for the GATE pad
> (another P would very neatly fit there).  The driver structure for P5 is
> also missing; for the 8500 and 8502, this will have to be different.  I'm
> guessing those do not have the GATE stuff and do have eight P pads and
> drivers; the only thing in the way for that is a test structure and the
> layer indicators ("0234567").

Are you able to determine the logic connected to the GATE_IN signal? 
Knowing that might allow it to be done by external logic and allow us to 
use a 6510 as a CPU. Since the port bits are different, that's only 
really an option for owners of a 1551 drive.



> What is different compared to the 6502...  Well, everything really!  The
> layout is quite similar, but all of it seems redone in some CAD thing.

Well, it was said somewhere that they redid the 6502 as a core to be 
able to create all the variants. Also, the 8501 uses HMOS-II, so 
everything should be smaller (at least that was the idea behind HMOS...)


> All the transistors are resized, many (all?) depletion pullups now use
> buried contacts.  All the pins on the 6502 were carefully close to where
> they were needed (like on the 6800, heh); on the 85xx not so, so there is
> a lot of busing inside the pad ring, taking up all the space where the
> drivers used to be.

Well, remember the 2 major differences between the 6502 and the later 
variants. First you have the AEC signal allowing you to tristate the 
address bus and some signals. That means changes to their drivers and at 
least one control signal to all of them. Second you have the I/O-Port 
residing on $0000 and $0001. That means you have to route all address 
signals to the access decoder for the port register and all data signals 
to the port itself. That should explain at least some of the extra 
traces near the pads.

  Gerrit


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