Re: Broken TED for visual6502.org

From: Segher Boessenkool <segher_at_kernel.crashing.org>
Date: Fri, 20 Jul 2012 09:16:04 +0200
Message-Id: <9A8EBFC6-83A8-43D0-9B07-620E06A37E0E@kernel.crashing.org>
>>> Could be... But what caused the driver for A7 to die in that fashion
>>> though? I should have tested all the signals before mailing in  
>>> the CPU
>>> to see if any of them were dead.
>>
>> A short circuit on the pin: if something (external) drives the  
>> address
>> line high while the CPU pulls it low, a nice big large current goes
>> through that big FET where the metal turned black.  It's not built
>> for such large currents, it's too high resistance for that, you get
>> heat, stuff melts and whatnot.
>
> The thing is, there have been external memory expansions for the  
> C16 that must have done exactly that with the _CAS line from TED  
> without killing it outright. The default is that the RAM in the C16  
> is mirrored 4 times and there is no way on the expansion port to  
> disable it. The only way to add another 16 KB on an external board  
> is to force _CAS for the internal RAM high at the proper address  
> space and generate your own _CAS for the RAM on the board.

I dunno.  Maybe they limit the current to some "safe" value.

The other thing is, as soon as the output FET is damaged it will have
higher resistance, accelerating the process.  Same thing as happens
with electromigration on metal tracks: small failure leads to big
failure.  It could well be that this failure started through
something else (your bad passivation theory, for example); but it
looks to me like it ended with a nice big current frying the thing.

>> Sure, I'd love to see those as well, but the 6510 has bigger  
>> differences
>> to both endpoints we have pics for so far (6502 and 8501).  And it's
>> historically more interesting.
>
> I expect it to be quite similiar to the 8501, just in NMOS since I  
> doubt they did a full relayout of the CPU from NMOS to HMOS.

We _know_ that the CPU core was redone somewhere between 6502 and 8501.
I find it more likely that it was done for the 8500 than that it was
already done for the 6510; esp. if you look at the actual layout on
the 8501, all the transistors are resized, so if it was already redone
for the 6510 it would have had to be redone twice.

We also know that all of the pad/drivers stuff is redone for HMOS: it
has to be much bigger relative to the core logic; you can see this on
e.g. the SID and VIC-II chips.

I don't expect the 8501 to differ much from the 8500 at all.  So if I
had to choose, I'd much rather see the 6510 than the 8500.  But we don't
have to choose, we'll see all of-em eventually :-)

Oh, and 7501...  :-)


Segher


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