Re: external ram expansion modules for 16k 264 series machines

On 2012-07-31 18:00, Gerrit Heitsch wrote:
> 
> You used a full 64K expansion for your tests. That one likely used 64Kx4
> DRAMs internally. So for that a fixed resistor would do. But there were
> also some 16K Expansions that only used 2 16Kx4 DRAMs, so it had to
> still use the internal DRAM.

Yes.

> Like those:
> 
> http://plus4world.powweb.com/hardware/C16_16K_RAM_Pack
> http://plus4world.powweb.com/hardware/16K_Expansion_Kingsoft
> 
> Interestingly, the extra logic is only 3 logic ICs and differs between
> the 2 cards. The small ceramic capacitors on the Kingsoft card suggest
> some timing hacks, probably to generate your own _CAS. Also there is a
> transistor and a 47Ohm resistor connected to it. That might be the
> _CAS-disabler.
> 
> The extra logic will have to detect $4000-$7fff (A15 low, A14 high),
> disable the internal RAM in that range by brute force and generate _CAS
> for the external RAM.

Well, first, the extra bank would have to be mirrored at $c000-$ffff
(otherwise, writes to $fffc...$ffff end up at $3ffc...$3fff instead of
$7ffc...$7fff which causes problems on a supposedly 32k-spec machine).
That makes A15 redundant, and incorporating CAS' (the TED's CAS', that
is) a must. IMHO this is, where things start getting tricky.

That said, I don't know how it's actually done.

One possibility is to store CAS' first, "kill" it if CAS'(stored) is low
and A14 is high, supply CAS'(stored) to the expansion ram; (and
obviously do neither if A14 is low). Then clear flip-flop by the rising
edge of RAS', MUX', or any arbitrary self generated signal. Something
like this might be suggested by the presence of the 74ls73 J-K
flip-flop. Problem is, an inevitable glitch on CAS' before the CAS'
killer is activated. I haven't checked whether that's problematic,
according to jedec ram spec. Regardless to that, it seems to be ugly.

Maybe the CAS' killer is activated if A14 is high, regardless to any
other conditions (A14 will have settled prior to CAS', that is, there'd
be no glitches). The tricky part is that CAS' is still needed for the
expansion logic, which needs to be restored from the then non-ttl
compatible, suppressed CAS' signal.

> Well, the C16 and C116 used only TMS4416 DRAMs (at least all I ever
> seen), so you only had to find a batch of DRAMs, maybe from a different
> maker that has better output drivers and can override the internal RAM.
> I can see no other way since the multiplexer will only supply the
> multiplexed addresses, there is no _CAS generator, no resistor to force
> _CAS high and they didn't do SMD back then, so there is no hidden logic
> on the back.

First, we seem to have an exception here (the C116 board I used for the
tests uses HM48416AP-12 ie. Hitachi drams, datecode 8432).

As for the memory expansion logic: I'm still a little bit reluctant to
believe that they just let 8 data lines to fight all the time in any
arbitrary dram cycles. (That must be a lot of current at the first
place, and second, we're still talking about NMOS dram chips that
supposedly have much weaker H than L drivers; that is, whichever the
type, the dram which stores 0 bits should probably win). But I'm not
sure, that is, until someone checks one of these expansion modules closely.


Levente

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