On 2012-10-09, at 17:22, Gerrit Heitsch wrote: >> 0. First 12 address bits change, A12 (13, 14) remains invalid >> 1. _CS goes LO, A12 (13, 14) remains invalid >> 2. Addresses are read and are being processed by the EPROM, A12 (13, 14) remains invalid >> 3. A12 (13, 14) changes >> 4. Correct addresses are read and start being processed, all address bits valid >> 4. Data pops up on the data bits (as per state in point [2.]) --> ERROR! >> 5. Next data show on data bits (as per state in point [4.]).. >> >> The question is how the EPROM behaves when addresses are changed within tACC - will it first deliver the data according to original addresses and then according to the new or will it discard the original and deliver the new only (albeit later)? > > The EPROM will first deliver the invalid data since it doesn't know anything about the change at the input. That's what I thought, when I first started thinking about the potential timing problem. > tAcc of an EPROM is the delay needed for the input signals to filter through the decoder, memory matrix and output drivers. (Assuming _CE and _OE are LOW) Does it have some sort of pipelining or does it have to deliver the data first, before reading next address? In other words for the scenario as above point [5.] is reached only after two tACCs (at most) or can it be like 1.1 tACC assuming that the last bits changed at 0.1 tACC? >> I was not sure but I tried to take A12 processing out of the equations by removing LS00 and delivering A12 directly to the EPROM (sockets of pins 2 and 6 shorted). Result: machine even less stable (sic!) > > And that's strange. If it was a too long delay, it should become more stable. If (I mean - IF) we talk timing problems here, this is indeed strange but not impossible. I mean instead of three bits being off schedule we now have two, which means we deliver somewhat else on the data bus than with all three off. This can affect how the machine behaves in various ways. Of course this is all speculations.. > Do you have a scope? No, I don't have any scope here, nor my saleae :-( > The interesting signal would be to trigger on _CS going low and display PHI0 and one of the data lines and see where the EPROM output changes state and what happens before and after. Yes.. wondering.. maybe you could quickly wire this circuit on a breakout board (should be less than half hour) and check how it behaves on your side? -- SD! Message was sent through the cbm-hackers mailing listReceived on 2012-10-09 18:01:12
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