Re: Weird pulses on KERNAL chip select line

From: Michał Pleban <*lists_at_michau.name*> Date: Mon, 10 Jun 2013 21:43:43 +0200 Message-ID: <51B62C6F.4030702@michau.name> · lists_at_michau.name

Hello!

John McKenna wrote:

> While AEC is high, the high address lines are pulled up by RP4.  When
> AEC goes low, it takes the processor a little time to start driving the
> address bus.  In this time, the address is $Fxxx and AEC is low, and
> that means a KERNAL access.
> 
> An RC filter followed by a schmitt buffer should fix it, as long as
> you're careful not to introduce too much delay.

I have no room on the PCB to accommodate an additional chip with Schmitt
trigger. But I think this would not be necessary.

I routed the KERNAL_CS line via a RC filter (R = 3.6 kOhm, C = 5 pF) and
ANDed this with original KERNAL_CS line. This makes sure that the
resulting signal starts a bit later than original (late enough to bypass
the pulses) but ends when the original ends.

The Flash now seems happy and responds properly to both reads and writes :-)

Regards,
Michau.

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