Re: DD2 & 3

On 06/18/2013 08:15 PM, Jim Brain wrote:
> On 6/18/2013 12:47 PM, Gerrit Heitsch wrote:
>> On 06/18/2013 07:38 PM, Jim Brain wrote:
>>
>>> I guess, but dubious.  CBM could have just went and stuffed something in
>>> the address map that contradicted the 6821 address space.  IN any event,
>>> it was an academic question.  Interesting that they sourced a 6821
>>> instead of just adding a '574/'245 or something simple.
>>
>> Replacing even a single port of a 6821 or a 6522 with TTLs only sounds
>> simple until you think about what this would really mean. I'd say a
>> 6821 or 6522 needs less space on the PCB than even a limited port
>> setup using TTLs in DIP that supports direction change of the data flow.
> If just a bidir parallel port was needed, I think a '138/245/574/04
> would have done the job, and could have been put in the same space.

Not quite since you also need to keep the direction information stored 
somewhere so that when the port is output, the data from stored in the 
574 will be visible on the outside after the CPU is done with it. On the 
other hand it must not put any data on the outputs if the port is to be 
used as an input. So you need a flipflop on _OE of the 574. Possibly 
half a LS74 and the logic to program it. This also means you'd be 
limited to the whole port being either input or output.


> also know cost was an issue, over board size.  Still,I can't imagine
> they didn't consider the option, and they did not pursue it.  Thus, it
> gives some additional weight to SD's position that they were looking far
> ahead, or they planned to use some feature in the 6821 in the near term.

Possibly the hardware handshake and IRQ capabilities. And the second 
port didn't hurt either in case someone came up with an idea for it.


> Like I said, interesting that they chose a full fledged PIA instead of a
> more tactical option.

The 6821 was quite cheap, compared to the 6522.

  Gerrit



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