Re: DD2 & 3

On 2013-06-18, at 19:21, Nicolas Welte wrote:

> Great to see the result, finally :D I didn't have time to read everything in detail, but in one place you even mention our conversiation about Dolphin. Nice :)

:-) I believe I owe you!

>> As I wrote there - for the pure 1541 use, whichever version ever appeared on the market eventually - it seems over-engineered to me no matter how I look at it ;-) See the lower address lines for example. DD2 gets along fine without touching anything below A11. In DD3 we have four additional gates to get A1 to A4 tapped on, leaving A0 untouched... I bet it would be much cheaper if the missing bit was put on a buffer [*]. For real reasons we would have to ask the creators themselves (I haven't found them on facebook yet ;-) but my best guess is that they wanted to be farsighted and less vulnerable to the whims of CBM than they were with the original design. Therefore they might have asked themselves the question "what if tomorrow Commodore takes more bits out or something?" "It's quite unlikely that they get rid of 6502 though so let's depend only on this one" - my guesses and speculations. Another thing is that they probably wanted the design to be applicable to many target devices without redesigning. No matter how laid out the controller's PCB is and whether there is a free port (be it VIA or CIA or whatever else) or not.
> 
> The same PCB was also used in the 1570 and 1571 versions of DD3, and even in the C128DCR version. The DCR drive has no free I/O lines at all, and the 1570/71 has only free lines on the CIA chip. To avoid having a different PCB for each 1541 version, and also for each 1570/1571/C128D/C128DCR version, they used the approach with the 6821 PIA.

I know that 1571 version existed but I have never seen it, let alone DCR version! Do you have access to those?

> Also, on another topic mentioned here, in my own 6502 RAM/ROM board for the 1541, I used 15ns Cache SRAM successfully with the DD2 system. Of course, my implementation of SRAM access is probably different.

Well... I checked what he wrote there and while the _CS and R/_W signals are processed in various ways on different controller's boards of the 1541 - (I might be missing something but) I still don't get it why could this affect the access of his own SRAM chip, unless his own processing of clock and r/_w got out of sync.
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