Re: FPGA/CPLD different approach

From: silverdr_at_wfmh.org.pl
Date: Mon, 26 Aug 2013 14:08:20 +0200
Message-Id: <D22B5628-A945-4135-8819-BD0E4D7B8CAF@wfmh.org.pl>
On 2013-08-25, at 20:08, Ed Spittles wrote:

> The Godil products are a big reason why I've found myself taking the Xilinx route.

I understand. What If I forget the CPU emulation and want to build only some RAM, ROM and one or two 8bit bi-directinal I/O ports, all available for the original CPU to interact with - what would you suggest? Can one easily make such structures (RAM, ROM, I/O port) available for 6502 from within a CPLD/FPGA and which would be "better" in such case?

-- 
SD!
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Received on 2013-08-26 13:00:18

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