Re: FPGA/CPLD different approach

On 2013-08-26, at 15:53, Ed Spittles wrote:

> If you mean to have the ROM/RAM on-chip, as opposed to hooking some up to an external address or data bus,

First I thought of putting inside everything, including the CPU itself. I thought of 6510 because it already has an I/O port but then I recalled that it is basically six bits only and I don't want to go serial. So I thought of putting in a 6502 and an extra I/O port but the more I read now, the more I am afraid that with my (lack of) experience in the field this bite can be too much to chew at once. At least for the first time. So the last idea is to use a real 6502 but give it some RAM, ROM and I/O inside the programmable IC. In other words I want the 6502 see all of the above on its address bus. I am not trying to catch up with Jeri (yet ;-) just want to give 6502 what it needs in order to both run and communicate with the outside world on a small footprint.

> you can certainly do that with Xilinx, and I think with others too.  The larger FPGAs have more available, but something like 24kbytes is the most you are likely to see - no chance of a full 64k memory map.

I don't need that much RAM. If I get 10KiB I'll be happy. If I try hard I can possibly even live with 4KiB.

> Although what you have onchip is RAM, you do get to define the initial contents at powerup, which makes it more like ROM if you do that, and if you like you can disallow writes, which makes it entirely like ROM.

I am not sure if I understand this. I read that I can have both, blocks of ROM and RAM inside an FPGA. But I am puzzled with the power-up. If I understand it correctly, the FPGA has to be "booted" from external ROM, which would probably mean that it /requires/ additional, non-optional chip outside. And only from that external ROM, I "configure" the FPGA again and again on every power-up, including the content of my ROM blocks inside the FPGA itself. But if I need an external ROM chip, I could possibly use it instead of trying to put ROM inside the FPGA. So if I remove ROM from the equation, there is RAM and I/O left. That should be possible with CPLD already. Eh..

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