On 2013-10-22, at 18:36, Gerrit Heitsch wrote: >>> As far as I know, with a 65xx-CPU, you need to incorporate PHI2 into the >>> R/_W signal (R/_W can only go LOW if PHI2 is HIGH), or is this already >>> done inside the MAX? >> >> Why would I want to do that, when I have a separate /CS signal for both >> chips? > > What's the latency in the _CS signal? The delay from the PLA and all the gates works the other way too, meaning even though the CPU is done and VIC has taken over the bus with AEC, the _CS signal will still be low for a time. Doesn't matter with a ROM, but with a RAM that can corrupt a write cycle. > > There is a reason why all simple 6502 systems I have seen (that includes the 1541) gate R/_W with PHI2 when talking to a SRAM. I noticed it too, and that's one of the things I kept asking myself about for some time. Would you be so kind as to elaborate on that reason? -- SD! Message was sent through the cbm-hackers mailing listReceived on 2013-10-22 18:03:35
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