On 06/11/2014 12:49 AM, Rainer Buchty wrote: > On Tue, 10 Jun 2014, Gerrit Heitsch wrote: > >> The problem is, as long as RESET is +10V, the datasheet claims ALL >> fetches are done via Port PC. So you cannot run a program from RAM >> until you return RESET to +5V. Catch-22... > > Actually, it claims that all *memory* fetches are made from Port PC. > > Whatever "memory" means here. Could be the entire memory range, given > that it's memory-mapped I/O, or just ROM (F)800-(F)FFF. The data sheet says clearly, that you can access the I/O that way: External test equipment can use this feature to test internal CPU logic and I/O. A program can be loaded into RAM allowing the contents of the instruction ROM to be dumped to any port fo external verification. But that might mean that you can only _write_ to any register, but any read (RAM, ROM, I/O) will only happen from port PC. Unfortunatly, the data sheet doesn't supply any more details but the term 'all memory fetches' suggests this being the case. Otherwise I would expect it to read 'all ROM fetches'. > Since the overall efforts in hardware are significantly lower for the > first case, i.e. only ROM (read) access is appearing at PCx, and given > that this simpler solution even makes debugging easier (as jumping to > 0000 would now fetch data from RAM, giving easy software control over > the ports), I wouldn't see the benefits of the "any access will come > from PCx", but maybe I'm missing something. To really know what's going on one would need a die shot. But I wouldn't be surprised if it was done as the datasheet hints. MOS did have experience with 10V-Test modes. See TED where 2 pins of the keyboard interface (K0 and K1) are used for to take TED into 2 test modes. (See TED data sheet) Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-06-11 15:00:03
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