On 07/01/2014 08:46 AM, Jim Brain wrote: > On 6/30/2014 12:17 PM, Gerrit Heitsch wrote: >> On 06/30/2014 07:13 PM, Gerrit Heitsch wrote: >> >>> The byte sequence for that is: >>> >>> 78 A9 55 85 83 xx 02 >> >> Mistake corrected here since SEI is 2 cycles: >> >> 78 xx A9 55 85 83 xx 02 >> >> >>> >>> EA EA EA EA EA EA EA EA EA EA 2C 24 EA xx 78 A9 55 85 83 xx 02 >> >> And here too: >> >> EA EA EA EA EA EA EA EA EA EA 2C 24 EA xx 78 xx A9 55 85 83 xx 02 >> >> >> Gerrit >> >> >> >> >> Message was sent through the cbm-hackers mailing list > No luck so far. PORT 0x83 always contains 0xfe... :-( > > I put the CPU back in the 1520 to ensure I did not roast it. > > I checked with the LA, always the same value... > > Will tackle more tomorrow. You made sure you supplied the bytes at half the speed of the clock you supplied to the 6500/1? Then there is, of course the question of phase. Since the external clock is divided by 2, there are 2 possible phases for the resulting clock signal the CPU runs on. So my idea is to get the external clock stable while keeping _RESET low, then have it go to +5V for a moment before going to +10V and start supplying the byte sequence. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-07-01 18:00:03
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