On Sat, Nov 29, 2014 at 01:20:14PM -0800, Nate Lawson wrote: > 2. Patents — the 65xx was designed by ex-members of the 6800 team. They reused some general ideas but improved on them. It would be interesting to see a side-by-side comparison of the two architectures. The general layout of the chip is much the same (PLA on top, "random logic" under it, then a row of big drivers for the ALU/bus/reg control; and under that, eight rows, one per bit, of the busses/regs/ALU; on the left and bottom of that address pins; on the right, data pins). The detailed implementation is very different, esp. the points the 6800 patents are about: state machines and bus structure. The 6800 uses many state machines, one per instruction (sort of kinda), implemented as delay lines with various taps feeding things. The 6502 uses a single cycle counter for everything (plus one extra state for interrupts, and two extra states for RMW insns); it decodes the time together with the insn opcode in the PLA. This only works (efficiently) if your ISA is more regular than the 6800's. With regard to bus structure, the 6502 uses more overlapping busses than the 6800 does (and curiously, the datasheets hide the existence of the "special bus"), and it can connect them together in more interesting ways. Segher Message was sent through the cbm-hackers mailing listReceived on 2014-11-30 01:00:03
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