Re: Question on Schematic

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Mon, 23 Feb 2015 11:10:17 +0100 Message-ID: <54EAFC89.7000308@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 02/23/2015 09:36 AM, Baltissen, GJPAA (Ruud) wrote:
> Hallo Gerrit,
>
>
>> Well. it should be...
>
> Just did dome googling and it seems I was wrong for all these years. But then again, why is the delay R/W signal at the beginning needed?

To make sure the addresses are really stable I'd think. Remember that 
PHI2 is slightly delayed compared to Phi0. The RAMs can get away without 
that delay since they don't care about addresses for writing until _CAS 
goes down which is rather late in the cycle. The CIAs use PHI2 directly.

  Gerrit

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