KiCad and decoupling capacitors help.

Over on http://www.vcfed.org/forum/showthread.php?48829-Commodore-8032-add-on-board-SuperPET I am documenting an add-on board I am designing to convert a bog-
standard Commodore 8032 PET into a SuperPET.

The intention is to make a PCB that plugs in place of the PET's 6502 CPU and can run both Commodore PET software and the 6809 languages of the SuperPET from the University of 
Waterloo. The addition of the TPUG MMU permits Super-OS/9 to be run (level 1 only) - and I have added a more extensive Memory Management Unit (an SN74LS610) to (hopefully) 
permit NitrOS-9 Level 1 and 2 to be ported to it. This is a much longer-term goal though.

I have developed (and refined) the requirements and have the schematic entered into KiCad - and exported to the PCB layout as a rats nest.

My immediate problem is what to do about the decoupling capacitors...

My PCB is four-layer with signal, power, ground and signal. However, no matter what I do, I always end up with the VCC pins of the ICs directly connected to the power plane - as I do 
with the VCC end of the decoupling capacitors. I have arranged the decoupling capacitors close the VCC pins of the IC but (as yet) I have found no way to persuade KiCad to let me 
rout a short length of thick PCB track from the IC VCC pins to the adjacent decoupling capacitors - where I am quite happy for the VCC pin of the decoupling capacitor to be 
connected to the VCC power plane via a thermal relief.

There doesn't seem to be anything in the manual or tutorials I can find. I have found a few similar questions - but either they go unanswered or there is an answer that doesn't seem 
to work (or is not detailed enough for the process to be followed)!

This would seem to be a pretty fundamental requirement for anyone designing a digital board (especially a CPU board) with KiCad.

Does anyone have any ideas how to help me out? I would like to get the simple things in life resolved before I start the hard task of routing the signal tracks!

Dave
 

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