Re: DATA BUS enable for IO0 on VIC-20

AFAIK the firmware roms (basic, kernal) don't get gated; they're on the bus
with the /BLK(1,2,3,5,6,7) areas.  The char rom and internal ram get gated
because the nmos 6502 doesn't have the ability to tristate its buses, and
the VIC chip needs the buses to get video data.  Since the character
bitmaps and internal ram are necessary to provide a working display they
have to be on the VIC side of the gates.

Why the I/O space is included is something I'm unsure about.  Likely a
cost-saving method since the VIC chip does have to be on the gated side of
the bus and it's also an I/O device in itself.


-David

On Fri, May 27, 2016 at 11:59 PM, Jim Brain <brain@jbrain.com> wrote:

> On 5/27/2016 2:45 AM, Segher Boessenkool wrote:
>
> On Fri, May 27, 2016 at 01:58:06AM -0500, Jim Brain wrote:
>
> It is late, and so I will admit I might have missed my answer, but I've
> pored over the schematics for the VIC-20 on zimmers for a bit and I
> can't see how the data bus '245 is enabled for the IO range (IO0, noted
> on the schematic).
>
> Maybe just because S02 is on?
>
>
> Segher
>
>        Message was sent through the cbm-hackers mailing list
>
>
> Yeah, I guess the fact that all of the other lines coming in messed me
> up.
>
>
> But, why gate the databus to all of the RAM and ROM areas?
>
>
> Jim
>
> --
> Jim Brainbrain@jbrain.com www.jbrain.com
>
>


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