Re: BBR/BBS 65C02 instruction cycle counts

From: Francesco Messineo <francesco.messineo_at_gmail.com>
Date: Fri, 1 Jul 2016 17:43:42 +0200
Message-ID: <CAESs-_z0jr-J7f_ULqh1VObvFCUokyX9jK-e-YJV7kjBeTOBpw@mail.gmail.com>
On Fri, Jul 1, 2016 at 4:22 PM, smf <smf@null.net> wrote:
> On 01/07/2016 15:21, smf wrote:
>>
>>
>> So an apple 2c probably would be fine, this manual mentions them.
>>
>>
>> http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Books/Gary%20B.%20Little%20-%20Inside%20the%20Apple%20IIc.pdf
>
>
> Sorry, my internet connection is dying with windows 10 insider previews. I
> was right, apple 2c doesn't have them.
>
> The manual mentions them by saying:
>
> "(The //c uses the version of the 65C02 produced by NCR Corporation. Another
> version, produced by Rockwell International Corporation, supports all of the
> NCR instructions and four additional ones called SMB (set memory bit), RMB
> (reset memory bit), BBS (branch on bit set), and BBR (branch on bit reset).
> You cannot use these instructions on the //c.) "
>

I confirm it's an NCR CPU on mine.
Frank IZ8DWF

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Received on 2016-07-01 16:00:01

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