Re: MAX Machine PLA equations

From: Segher Boessenkool <*segher_at_kernel.crashing.org*> Date: Fri, 5 Aug 2016 20:20:32 -0500 Message-ID: <20160806012032.GG19380@gate.crashing.org> · segher_at_kernel.crashing.org

The I/O part becomes

===
T := (BA or RW_IN) and CLK0

if (T) {
	not #VIC    := A15..A10=110100
	not #SID    := A15..A10=110101
	not #COLRAM := A15..A10=110110
	not #CIA    := A15..A10=110111
} else {
	not #VIC    := A15..A10=110100 and CLK0
	not #SID    := 0
	not #COLRAM := CLK0
	not #CIA    := A15..A10=110111 and CLK0
}

RW_OUT := not T
===

which seems sane, except for the VIC accesses to VIC and CIA.  What
drives A15,A14 during such accesses, anyway?

Segher

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