Re: DRAM refresh

From: Segher Boessenkool <*segher_at_kernel.crashing.org*> Date: Sat, 15 Oct 2016 13:38:49 -0500 Message-ID: <20161015183849.GB29997@gate.crashing.org> · segher_at_kernel.crashing.org

On Sat, Oct 15, 2016 at 06:49:45PM +0200, Gerrit Heitsch wrote:
> >>AFAIR the VIC-II row counter for refresh is free-running.  I'll have
> >>a look later.
> >
> >It is reset at the end of the frame, actually.
> 
> I wonder why they do that... Making sure that the counter can't get 
> stuck somehow?

Probably.  The VIC-II does not have an external reset signal; instead,
most blocks rely on being reset some other way, usually from the frame
timing.  The first frame output can be very, uhh, interesting.  This
may be another reason why they opted for a separate (from matrix fetch)
refresh, btw.

Another reason to reset the refresh counter every frame is to make sure
all frames are alike, which might help validation etc.

Segher

       Message was sent through the cbm-hackers mailing list