On 17/02/2017 20:26, Gerrit Heitsch wrote: > That can be fixed by using a static RAM instead of DRAMs. It can be fixed by latching signals as well. My point is that a 100% VIC II in an FPGA would have the VSP problem, or it's not 100%. AFAIK vice doesn't have the VSP problem either. Message was sent through the cbm-hackers mailing listReceived on 2017-02-18 09:00:02
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