On 11/2/2017 9:52 AM, Mia Magnusson wrote: > > Is there really more than sending 8 clock pulses and drive the data > line? Of course with the correct polarity of all stuff e.t.c. It's less a about when to send the $ff. and more about when *NOT* to. And, sending the $ff is trivial. It's watching for the $ff indicator on the computer side * 8 ports at the correct time, and then ignoring other $ff signals at any other time. Again, it's not insurmountable, but you either need to build 8 sets of TTL logic to correctly watch for the indicator on the 8 incoming ports (and ignore any other time), you need to use a microntroller that can watch the 8 CLK lines at the correct time, or you need to implement the functionality in a PAL/GAL/CPLD. I found that a 16MHz uC could not satisfactorily watch the CLK lines for activity, and I had no desire to bulk up on TTL in the board, so I decided to learn Verilog so I could implement the required functionality. JIm Message was sent through the cbm-hackers mailing listReceived on 2017-11-02 18:00:03
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