On 11/24/2017 07:28 PM, Francesco Messineo wrote: > On Fri, Nov 24, 2017 at 7:08 PM, Gerrit Heitsch > <gerrit@laosinh.s.bawue.de> wrote: >> On 11/24/2017 07:00 PM, Francesco Messineo wrote: >>> >>> Hi all, >>> I'm going to repair a PET 2001, the board with 6540 ROMs and 6550 RAMs. >>> I'm still in the phase of studying the schematics to understand this >>> particular design. >>> Now, I'm not really getting why the R/W signal to all the RAMs, >>> including the two video RAMs is ANDed with the /SELE signal, can >>> anyone shed some light here? >> >> >> /SELE? If that means PHI2, then it's just what you usually need to do in a >> 6502 system. R/W can only gow LOW, meaning a write cycle, as long as PHI2 is >> HIGH. If you don't do it this way, you will corrupt the data in RAM. > > PHI2 is PHI2 and goes to the corresponding pin of the 6550s. /SELE is > well... /SELE and > comes from a 4 to 16 decoder having A15..A12 as inputs. It should be > low when A15..A12 is 0xE. So that means that R/W at the RAMs would go low when $E000-$EFFF appears on the address bus. Otherwise it would just reflect the state of R/W from the CPU. No idea what that could be used for since the /CS lines for the RAMs will keep them inactive in that range. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2017-11-24 19:03:05
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