Re: testing 6550s outside a 6502 bus

From: Francesco Messineo <*francesco.messineo_at_gmail.com*> Date: Fri, 5 Jan 2018 17:08:43 +0100 Message-ID: <CAESs-_y6SKRE4fMK_5ncviURXLi2ODQe0B9bqokhFZgLSgvgZA@mail.gmail.com> · francesco.messineo_at_gmail.com

On Fri, Jan 5, 2018 at 3:40 PM, Gerrit Heitsch
<gerrit@laosinh.s.bawue.de> wrote:
> On 01/05/2018 01:36 PM, Francesco Messineo wrote:
>>
>> On Thu, Jan 4, 2018 at 7:19 PM, Francesco Messineo
>> <francesco.messineo@gmail.com> wrote:
>>>
>>> On Thu, Jan 4, 2018 at 7:09 PM, Gerrit Heitsch
>>> <gerrit@laosinh.s.bawue.de> wrote:
>>>>
>>>> On 01/04/2018 06:56 PM, Francesco Messineo wrote:
>>>>>
>>>>>
>
>
>
> I'd look at the timing diagram for the 6502 write cycle and try to replicate
> it as close as possible. Onky change the timing once you get successful
> reads and writes.

according to the datasheet, write data are stable after phi2 rising
edge to after the falling edge, as I did.

Frank

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