On 5/8/2018 12:23 AM, And Fachat wrote: > > > Am 8. Mai 2018 02:20:11 schrieb Jim Brain <brain@jbrain.com>: > >> >> I am keenly interested in MMU design, since I am working on one for >> another platform. >> > > FYI, here http://www.6502.org/users/andre/hwinfo/ls610/index.html I > built a replacement for the 74ls610 MMU using cache RAM, where most > address lines are kept zero. I referenced your design as I worked on some designs, so a belated thanks. > > I use the ls610 in my system to map 16 pages of 4k from a 1MB physical > address space. But external logic is used to have the MMU (all IO) > available in all mappings, and to have a defined state at reset. Also > the upper 4 bits of the MMU are used as write protect, valid and > NoExecute bits. Still 4 data bits of one of the cache RAMs are unused > and could be used as additional address lines. I decided to implement my MMU in a CPLD with a fast SRAM for the "mapping" registers, and extended it to 16 bits, using the top 3 bits as you do. > > Using a task register for more of the address bits would indeed allow > quickly switching between mappings. But extra logic should probably be > included for shared memory windows on top or for IO to avoid > trampoline code etc. But IO could also be protected from some mappings > for "unprivileged" programs. The CPLD provides that capability easily. The current features are: 5 bit task register (32 main tasks) 8 16 bit values per task (8kB mapping granularity, >2MB address space capable) optional common RAM area 7 bits of "secondary task" capability (multiple mappings per task, etc.). Jim > > Regards > André > > > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-05-08 21:00:05
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