Re: MMU prototyping

Hello!

Just out of curiosity, does it work on the actual Ultimax too? And if
yes, where does the 2 kB of RAM at $0800 come from in this configuration?

Regards,
Michau.


Jim Brain wrote:
> It's a bit tough for me to prototype things on the B series, but I have
> been playing around with MMU functionality on the C64.
> 
> First, for those who have helped me understand the Ultimax mode, I owe
> many thanks.  For the longest time, that mode just completely baffled
> me. I am still not sure I completely understand it, but I have been able
> to tame it, at least a bit.
> 
> Secondly, perhaps this is heresy, but I particularly like the MMU in the
> Color Computer 3, so I am working to replicate it on the C64
> 
> I also like the LCR/PCR functionality of the C128 MMU, so I am also
> borrowing that as well.
> 
> I started by implementing the much maligned GeoRAM system in the CPLD,
> which was trivial.  So, I have HDL for GeoRAM now.
> 
> I then decided to implement an Ultimax memory expansion system:
> 
>   * In this mode, the memory map is split into 4kB pages
>   * Each page except for 0 and D can be directly mapped to external RAM
>   * To map a C64 page to external RAM, simply store the mapped page
>     number into the slot for that page.
>       o For example, to map $c000-$cfff to the 4th 4kB RAM block in
>         external RAM, store a 3 into MMU slot 12
>       o Any slot with 0 will map to internal RAM
>   * The system supports 256 sets of mappings.  Change the mapping by
>     storing a new value in the "task" register
> 
> The Ultimax mode was actually pretty simple to add, but it took a while
> to sort out a few bugs with the multiplexed memory address/data bus. 
> Still, it looks to be working at this point.  I am only pushing CPU
> access to external RAM, but I think I can do the same for VIC-II access. 
> 
> I did also use one of those clock multiplier PLLs I've had sitting in
> the parts box for a long time, to multiple the dot clock by 8 in order
> to see how well those work.
> 
> The system contains 2 types of RAM:
> 
>   * 512kB SRAM
>   * 32kB SRAM
> 
> The second SRAM holds the mmu mappings, since the CPLD is not large
> enough to hold them.  The 32kB SRAM is a 15nS part, so I multiplex the
> memory address bus:
> 
>   * As phi2 goes high, I start counting fast clock cycles (~64MHz, or
>     15ns per clock cycle)
>   * at count 2 and 3, I turn on 32kB SRAM and read mapping, using
>     address: {task:address_cpu[15:12]}
>   * at count 4, I acquiesce the memory bus for 15ns
>   * at count 5+, I select either the 32kB SRAM (MMU mapping read or
>     write) or the 512kB SRAM (regular memory access)
> 
> Left to add:
> 
>   * Add support for 16 LCR locations, mapping to the first 16 tasks.
>   * Fix clock signal to use EasyFlash/EasyFlash3/Swiftlink clock circuitry
>   * clean up memory usage (for registers)
>   * See about possibly supporting VIC access.
> 
> Ideas always appreciated.  Obviously, this new mode is compatible with
> nothing, but it's far faster than either GeoRAM and REU.  There's
> probably not room to add REU support as well, but I am going to try my
> hand at a standalone HDL REC implementation elsewhere.
> 
> Jim
> 
> -- 
> Jim Brain
> brain@jbrain.com 
> www.jbrain.com
>