Cascading 2-bit up/down counter

I have been looking at a certain counter,

Cascading 2-bit up/down counter

I searched on Wikipedia and it says Cascading is done with a Shift register.
This uses an SR Flip flop, so two SR flip flops and a few other components
but will an SR Flip Flop count up/down
does it need to be Bi directional?

I'm using the free Altera FPGA software that supports CPLD
it seems this can simulate older gates and test them and add these to
the older library.

I tried this for the fun of it and I made a simple older MUX. ☺


The CBM CMOS chip I'm working on the spec sheet in a few gates
mentions "GATING" inputs and outputs, what does this mean exactly?

I was really wondering what part I could start out with to then make my own
SR flip flop.

I assume the GATING inputs and outputs in certain gates would have to be
simulated
and made this way, if unavailable.

Altera has an older primitive library but no listing for SR flip flops.

Im still in a learning curve did some reading though on Cascading and it
seems I
was using the wrong Flip Flop.

Terry Raymond