Den Sun, 10 Jun 2018 16:00:46 +0200 skrev Gerrit Heitsch <gerrit@laosinh.s.bawue.de>: > On 06/10/2018 03:47 PM, Michał Pleban wrote: > > Gerrit Heitsch wrote: > > > >> Might not be possible since the 6525 has NMOS output drivers which > >> allow you to do things that you can't do with CMOS output drivers. > >> Namely having 2 outputs (one LOW, one HIGH) directly connected. > > > > The only role the 6525 has on the board is to connect to the 6526 > > on the other side to pass some signals. > > > > So what we thought to do was rather implement *both* the 6525 and > > 6526 in the CPLD, or more precisely, only these parts which are > > necessary for this particular interface. Then the CPLD would be > > directly connected to the 8088 bus on one side and 6509 bus on the > > other side. I don't know about 8088, but I have already connected a > > CPLD to the 6509 before and it worked like a charm. > > Another Idea would be to use an AM2130 (datasheet is available > online) or similiar chip instead if you can find them. That's a 1k x > 8 dualport RAM with built in arbitration. Should be perfect to > interface 2 systems. In a hypothetical perfect world, we would recreate the B series motherboard and use far faster RAMs, making it possible for both CPU's to access the RAM seemingly simultaneously (but in fact of course sequentially but invisible to the user). -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-06-12 18:02:24
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