Den Tue, 12 Jun 2018 15:08:02 -0500 skrev Jim Brain <brain@jbrain.com>: > On 6/12/2018 2:24 PM, David Wood wrote: > > TL;DR - > > A RMW operation should be possible without modifying anything but > > the r/w signal on the bus according to most FPM datasheets I've > > studied, but would require some pretty good timing to ensure the > > VIC-II has completed its CAS cycle since the cart has to run blind > > relative to RAS and CAS. It's already capable of counting DOT > > cycles so that should be easy. > I thought the VIC-II did the CAS cycle during PHI2=low half of the > cycle. I can put it on the LA tonight, but is there a diagram > already available showing the signals? Not 100% sure how it is done, but there must be some "pause" with both RAS and CAS high between VIC and CPU access to ram, so you shouldn't count on having a full half period of the 1MHz clock for memory access, but slightly less. But that maybe eqauls to CAS asserted halfway through a 1MHz half cycle? -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-06-13 00:01:08
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