Re: DMA successes with Verilog

On Tue, Jun 12, 2018 at 05:46:22PM -0400, David Wood wrote:
> On Tue, Jun 12, 2018 at 4:08 PM, Jim Brain <brain@jbrain.com> wrote:
> > I thought the VIC-II did the CAS cycle during PHI2=low half of the
> > cycle.    I can put it on the LA tonight, but is there a diagram already
> > available showing the signals?
> 
> I'm not aware one that anyone has officially published.  I think Zero-X had
> done a timing grab at high resolution when trying to figure out how memory
> corruption occurs during a VIC-II DMA restart though.  If that's still in
> the wild it could be used to gather information.
> 
> It's probably simpler to just grab your own sample.  Publishing what you
> find would be really interesting to see. :)
> 
> That said, there has to be a RAS/CAS sequence during PHI2=low so the VIC-II
> can read graphics data from memory.  During text mode I believe most
> accesses usually head for the ROM, but with a RAM charset or bitmap mode
> that wouldn't be the case.
> 
> A second RAS/CAS sequence has to occur during PHI2=high to complete a
> transaction for the CPU.

CAS is active for approximately the first half of both PHI2 high and low.

Second line in
http://segher.ircgeeks.net/c64/plots/vic-old.html

(And see
http://segher.ircgeeks.net/c64/plots/vic.html
for why Gerrit made these plots: we were looking at the "grey pixel
noise" thing.  All these plots are his.)


Segher