Re: DMA successes with Verilog

On 14/06/2018 22:29, Mia Magnusson wrote:
>
> Why does the badlines work while you supposedly cant DMA any time you
> want? (Assuming DMA is synchronised to the clock)?
Supposedly this

https://groups.google.com/d/msg/comp.sys.cbm/wdVBsz16qLw/CcxIRuZF8xgJ

 > Pull the DMA line low (pin 13 on the expansion port), then the 6510
 > puts it's bus lines into a high impedance state, no need to worry about
 > the 6510 executing anything!

But think twice before pulling down DMA. The C64's memory management
system is well designed for non-external-DMA operation, but if using
external DMA it isn't 100% bug free!

The problem is the handling of the three phi2 cycles after the 6510's
READY input is pulled down. In read mode the NMOS6510/8500 will stop
immediately, in write mode it will stop after the last write cycle, but
not without setting its address lines to the next address!

No problem if the next address is a RAM/ROM location, but big problem if
this address refers to an IO chip, especially an interrupt flag register.
In worst case this register is read 3 times by the frozen 6510 and 1 time
after the DMA when the 6510 fetches the data.

To avoid any problems with this IO insecurity the C64 developers used a
brilliant but ugly hack: They advised the PLA to redirect any IO read
accesses to the internal RAM regardless of $01 in these 3 cycles!

But the PLA hasn't the ability to count 3 cycles (it's a dump logic
array), so they implemented this protection for the VIC's DMA only.
There's a simple way to detect these 3 cycles - just when R/-W is high, BA
is low and AEC is high. That's the only reason why BA is connected to the
PLA.

So external DMA hasn't such protection and if you pull down DMA just
before the 6510 wants to read something from an IFR the IFR is read before
and after DMA. For 'normal' applications this may never be a problem, but
if you want the C64 to do highly sophisticated interrupt stuff combined
with external DMA you will risk a systematic failure.

This is a brain dead design failure of the C64. Almost so brain dead like
the 6502/10's failure to forget the BRK opcode jump when IRQ/NMI goes down
executing the first few cycles of BRK.

MfG Andreas