On 6/15/2018 9:42 AM, Francesco Messineo wrote: > that would be actually only 16 macrocells. One of the examples on > WinCupl makes 3 x 8 bit ports with DDR on a 32 macrocells CPLD, so the > same macrocell it's been used for the port bit and its DD bit > (probably different functions of the same FF). > The result doesn't change much I think. I can't see how that would work. You need 2 stateful cells per IO pin for this use, and MCs only have 1 flop. Maybe they did a byte wide DDR (1 bit for the entire byte of data). Can you share a link to the specific CUPL example so we can see how they implemented it? > > By the way, does a 6502 really need a transceiver on the data bus? > Does it still drive the data bus during the low clock phase? I thought it goes read-only, but doesn't the 7501 allow the databus to be tristated during phi high? > > > F > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-06-16 02:01:31
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