On 6/16/2018 1:03 AM, Gerrit Heitsch wrote: > On 06/16/2018 07:29 AM, Jim Brain wrote: >> If NMOS drives hard to ground and not very hard to +5V, you *might* >> be able to get by with letting the pins float high via 1K resistors >> and drive only to ground with the CPLD (Xilinx has tristate output >> buffer options, and I am sure the rest do as well) > > Unfortunatly, that would increase power consumption by quite a bit. 16 > I/O with 1 KOhm set to LOW would be 80 mA just for the I/O. > > Gerrit > > I posit it would not. Some nice CMOS CPLD would draw very little for internal switching, and the NMOS 6526 used 100mA. If you disagree, that's OK, but something has to give. Either let it draw more A, or bulk it up with more ICs to handle the assymmetric drive, which will drive up cost and power as well. Maybe do 2K2 to balance the draw, or assume that IO would be driven 50% of the time, meaning ~40mA of drive. I used 1K as a stand in for "some resistance low enough to preserve the slope of a high value on a pin, but high enough to allow the pin to be driven low by the CPLD". Work with me here. Jim -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-06-16 09:00:16
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