Hello! Jim Brain wrote: > The current code will not work on the previous board. The previous > board did not sit in between the Data path. This one does. I understand that, but I just want to look at the current Verilog code because otherwise I will have no idea what is causing the errors. Generally it looks like the four topmost bits are set to 1 but not always (because read bank direct 1 passes OK), without the actual hardware in hand I can only deduce the cause by looking at the Verilog. Also please post the results of the tests from the previous board - do they differ in any way from the current board? Regards, Michau.Received on 2018-06-28 21:00:25
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