An update: I have revised the PCB design (v4) to support the NMOS 6502, the CMOS 65C02(S), and the WDC W65C816S CPU. A jumper on the PCB configures the CPLD for proper operation. The WDC '816, with VPA and VDA pins, makes the job of handling the 6509 behavior much easier. The system uses the E pin on the '186 to interpret setting the port pins: If E is high (emulation mode) or the CPLD is configured for '02 use, the port pins match the 6509 behavior If E is low AND the CPLD is configured for '816 operation, PORT = lower 4 bits of the bank register. The upper 4 bits are placed on some jumper pads. All pins except for the SO pin and the PHI2 OUT pins are mapped. I am checking the schematics to see if those pins need to be mapped. JimReceived on 2018-07-16 07:00:04
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