On 7/17/2018 1:31 AM, Baltissen, GJPAA (Ruud) wrote: > I really like that :) That would give me the 65816 I always liked to have. It does mean that the Kernal has to be rewritten but I wouldn't mind. Well, it should not *HAVE* to be rewritten. It can, though, to support the '816. > > May I politely point you to something? In the early days I equipped a VIC-20 with a 65816 and an ISA expansion. After building the whole thing I found out that I had misunderstood the behavior of the RDY input. Negating RDY does stop the 65816 from performing any instruction but does NOT stop it from outputting the content of the bank register on to the data bus when E is (L). > > In time I found a solution by keeping the clock input (H) during the time RDY was (L). You'll find the schematic at: > > http://baltissen.org/newhtm/65sc816.htm > > I hope this is some help. The existing logic puts the data lines in a HiZ state when PHI2 is low. This should eliminate the problem. I have successfully implemented smf's idea. When '(C)02 behavior is selected, 6509 !SO is connected to 6502 pin 38 and sync line is pulled from pin 7. PORT pins 0-3 represent $0 and/or $1 based on opcode. Port pins 4-7 are currently 0. When '816 behavior is selected, 6509 !SO line is connected to !ABORT and sync line is generated from VPA & VDA. Port pins 0-3 represent $0/$1 when E is high, and bank address when E is low. PORT pins 4-7 are connected to 0 when E is high, and bank address[7:4] when E is low. Question: On a real 6509, if you store $aa at $0 and read it back, do you get $0a or $aa? JimReceived on 2018-07-18 08:00:04
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