On 7/18/2018 3:25 AM, Baltissen, GJPAA (Ruud) wrote: > Hallo Jim, > > >> The existing logic puts the data lines in a HiZ state when PHI2 is low. This >> should eliminate the problem. > What if something negates RDY because it is a slow device and reads the data the moment PHI2 is low? That was the trouble I ran into with my 65816 equipped VIC-20; instead reading the data it read the bank address. In your case it finds a tri-stated data bus w/o data, no good either. I am reluctant to implement something that does not match the timing diagram on the datasheet. Data should only be valid on the high phase of PHI2. > AFAIK a 6509 also outputs the data when PHI2 is low so if you want to be compatible, your device should do as well. I feel that is more a function of the native delay inherent to NMOS devices. I doubt the data is presented on the pins for very long during the low phase of the cycle Emulating that behavior means incorporating a fast clock (50MHz or so) on board, to create a sub 1MHz signal that can be used to place the data on the bus past the time that PHI2 falls. I can incorporate part of this functionality by setting the IO pins on the CPLD to have a slow skew, which I will do. Hwoever, adding a clock signal requires an IO pin, and I have officially used all 52 available IO pins. Of course, the design is open source, so someone can modify it to suit other needs. JimReceived on 2018-07-18 20:02:48
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