Those internal operations were speculation. I remember JSR being one of the more baffling instructions - Marko and I had a long discussion about it, of which I remember none of the details, except for a feeling that we hadn't ever really understood it. Now that we have Visual6502, it should be possible to find out the truth. ________________________________ From: Ruud@Baltissen.org <Ruud@Baltissen.org> Sent: 19 September 2018 14:26 To: cbm-hackers@musoftware.de Subject: Error in 64doc.txt at Bo's site? Hallo allemaal, I'm building two TTL CPUs right now. For those who have no idea what I mean, have a look here: http://homebrewcpuring.org/ Please have a look at: http://www.6502.org/users/dieter/m02/m02.htm and http://www.6502.org/users/dieter/m02/system.jpg Notice that this computer only emulates the C64 more or less. My first TTL CPU has no Instruction Decoder which means every action that the CPU has to do has to be programmed. Advantage: you need less parts, disadvantage: you need (roughly) about ten times as much memory and it is twenty times as slow. The second one has an Instruction decoder (ID) and should be able to emulate the 6502, although not cycle exact. The ID is made from seven FlashRAMs and needs to be filled with data of course. For this I am writing a program that analyses every step of every instruction and then sets or resets the according bits of the involved FRAM. Now at this moment I am dealing with JSR. Next is the text for JSR from 64doc.txt found on Bo Zimmers site: # address R/W description --- ------- --- ------------------------------------------------- 1 PC R fetch opcode, increment PC 2 PC R fetch low address byte, increment PC 3 $0100,S R internal operation (predecrement S?) 4 $0100,S W push PCH on stack, decrement S 5 $0100,S W push PCL on stack, decrement S 6 PC R copy low address byte to PCL, fetch high address byte to PCH What I read is: at step 1 and 2 the Program Counter is increased and thus points to the next instruction at step 4. So this is the address that is pushed to the stack at step 4 and 5. But IMHO the PC is only incremented once before pushed to the stack. When RTS is executed, the stored address is read, written into the PC and increased according this document. Which prooves the incremental at step 2 is wrong. Your comment, please. -- Kind regards / Met vriendelijke groet, Ruud Baltissen www.Baltissen.orgReceived on 2018-09-20 22:00:05
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